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cy7c1021d 1-mbit (64 k 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05462 rev. *j revised june 7, 2011 1-mbit (64 k 16) static ram features temperature ranges: ? industrial: ?40 c to 85 c pin and function compatible with cy7c1021b high speed ? t aa = 10 ns low active power ? i cc = 80 ma at 10 ns low cmos standby power ? i sb2 = 3 ma 2.0 v data retention automatic power down when deselected cmos for optimum speed and power independent control of upper and lower bits available in pb-free 44-pin 400-mil wide molded soj and 44-pin tsop ii packages functional description the cy7c1021d is a high performance cmos static ram organized as 65,536 words by 16 bits. this device has an automatic power down feature that significantly reduces power consumption when deselected. the input and output pins (io 0 through io 15 ) are placed in a high impedance state when the device is deselected (ce high), outputs are disabled (oe high), bhe and ble are disabled (bhe , ble high), or during a write operation (ce low and we low). write to the device by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (io 0 through io 7 ), is written into the location specified on the address pins (a 0 through a 15 ). if byte high enable (bhe ) is low, then data from i/o pins (io 8 through io 15 ) is written into the location specified on the address pins (a 0 through a 15 ). read from the device by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appears on io 0 to io 7 . if byte high enable (bhe ) is low, then data from memory appears on io 8 to io 15 . see the truth table on page 10 for a complete description of read and write modes. 64k x 16 ram array io 0 ?io 7 row decoder a 7 a 6 a 5 a 4 a 3 a 0 column decoder a 9 a 10 a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 2 a 1 io 8 ?io 15 ce we ble bhe a 8 logic block diagram [+] feedback
cy7c1021d document #: 38-05462 rev. *j page 2 of 16 contents pin configuration ............................................................. 3 selection guide ................................................................ 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 switching characteristics ................................................ 6 data retention characteristics ....................................... 7 data retention waveform ................................................ 7 switching waveforms ...................................................... 7 truth table ...................................................................... 10 ordering information ...................................................... 11 ordering code definitions ..... .................................... 11 package diagrams .......................................................... 12 acronyms ........................................................................ 14 document conventions ................................................. 14 units of measure ....................................................... 14 document history page ................................................. 15 sales, solutions, and legal information ...................... 16 worldwide sales and design s upport ......... .............. 16 products .................................................................... 16 psoc solutions ......................................................... 16 [+] feedback
cy7c1021d document #: 38-05462 rev. *j page 3 of 16 pin configuration figure 1. 44-pin soj / 44-pin tsop ii (top view) [1] selection guide description -10 (industrial) unit maximum access time 10 ns maximum operating current 80 ma maximum cmos standby current 3ma 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 5 18 17 20 19 27 28 25 26 22 21 23 24 a 6 a 7 a 4 a 3 a 2 a 1 a 0 a 14 a 15 a 8 a 9 a 10 a 11 a 12 a 13 nc nc oe bhe ble ce we io 0 io 1 io 2 io 3 io 4 io 5 io 6 io 7 io 8 io 9 io 10 io 11 io 12 io 13 io 14 io 15 v cc v cc v ss v ss nc 10 note 1. nc pins are not connected on the die. [+] feedback
cy7c1021d document #: 38-05462 rev. *j page 4 of 16 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied ... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v cc to relative gnd [2] ................................?0.5 v to +6.0 v dc voltage applied to outputs in high z state [2] ................................ ?0.5 v to v cc + 0.5 v dc input voltage [2] ............................ ?0.5 v to v cc + 0.5 v current into outputs (low) .... .................................... 20 ma static discharge voltage ......................................... > 2001 v (per mil-std-883, method 3015) latch up current ................................................... > 200 ma operating range range ambient temperature v cc speed industrial ?40 ? c to +85 ? c 5 v ? 10% 10 ns electrical characteristics over the operating range parameter description test conditions -10 (industrial) unit min max v oh output high voltage i oh = ?4.0 ma 2.4 ? v v ol output low voltage i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.2 v cc + 0.5 v v v il input low voltage [2] ? 0.5 0.8 v i ix input leakage current gnd < v i < v cc ? 1+1 ? a i oz output leakage current gnd < v i < v cc , output disabled ? 1+1 ? a i cc v cc operating supply current v cc = max, i out = 0 ma, f = f max = 1/t rc 100 mhz ? 80 ma 83 mhz ? 72 ma 66 mhz ? 58 ma 40 mhz ? 37 ma i sb1 automatic ce power down current ?ttl inputs max v cc , ce > v ih , v in > v ih or v in < v il , f = f max ?10ma i sb2 automatic ce power down current ?cmos inputs max v cc , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v, or v in < 0.3 v, f = 0 ?3ma note 2. v il (min) = ?2.0 v and v ih (max) = v cc + 1 v for pulse durations of less than 5 ns. [+] feedback
cy7c1021d document #: 38-05462 rev. *j page 5 of 16 capacitance parameter [3] description test conditions max unit c in input capacitance t a = 25 ?? c, f = 1 mhz, v cc = 5.0 v 8 pf c out output capacitance 8pf thermal resistance parameter [3] description test conditions 44-pin soj 44-pin tsop ii unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four-layer printed circuit board 59.52 53.91 ? c/w ? jc thermal resistance (junction to case) 36.75 21.24 ? c/w ac test loads and waveforms figure 2. ac test loads and waveforms [4] 90% 10% 3.0 v gnd 90% 10% all input pulses * capacitive load consists of all components of the test environment rise time: ?? 3 ns fall time: ?? 3 ns 30 pf* output z = 50 ? 50 ?? 1.5 v (b) (a) 5 v output 5 pf (c) r1 480 ?? r2 255 ?? high-z characteristics: including jig and scope notes 3. tested initially and after any design or process changes that may affect these parameters. 4. ac characteristics (except high z) are tested using the load conditions shown in figure 2 (a). high z characteristics are tested for all speeds using the test load shown in figure 2 (c). [+] feedback
cy7c1021d document #: 38-05462 rev. *j page 6 of 16 switching characteristics over the operating range parameter [5] description -10 (industrial) unit min max read cycle t power [6] v cc (typical) to the first access 100 ? ? s t rc read cycle time 10 ? ns t aa address to data valid ? 10 ns t oha data hold from address change 3 ? ns t ace ce low to data valid ? 10 ns t doe oe low to data valid ? 5 ns t lzoe oe low to low z [7] 0?ns t hzoe oe high to high z [7, 8] ?5ns t lzce ce low to low z [7] 3?ns t hzce ce high to high z [7, 8] ?5ns t pu ce low to power-up 0 ? ns t pd ce high to power-down ? 10 ns t dbe byte enable to data valid ? 5 ns t lzbe byte enable to low z 0 ? ns t hzbe byte disable to high z ? 5 ns write cycle [9] t wc write cycle time 10 ? ns t sce ce low to write end 7 ? ns t aw address setup to write end 7 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 7?ns t sd data setup to write end 6 ? ns t hd data hold from write end 0 ? ns t lzwe we high to low z [7] 3?ns t hzwe we low to high z [7, 8] ?5ns t bw byte enable to end of write 7 ? ns notes 5. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 6. t power gives the minimum amount of time that the power supply should be at typical v cc values until the first memory access can be performed. 7. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 8. t hzoe , t hzbe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in (c) of figure 2 on page 5 . transition is measured when the outputs enter a high impedance state. 9. the internal write time of the memory is defined by the overlap of ce low, we low and bhe /ble low. ce , we and bhe /ble must be low to initiate a write, and the transition of these signals can terminate the write. the in put data setup and hold timing should be referenced to the leadi ng edge of the signal that terminates the write. [+] feedback
cy7c1021d document #: 38-05462 rev. *j page 7 of 16 data retention characteristics over the operating range parameter description conditions min max unit v dr v cc for data retention 2.0 ? v i ccdr data retention current v cc = v dr = 2.0 v, ce > v cc ? 0.3 v, v in > v cc ? 0.3 v or v in < 0.3 v ?3ma t cdr [10] chip deselect to data retention time 0 ? ns t r [11] operation recovery time t rc ?ns data retention waveform 4.5 v 4.5 v t cdr v dr > 2 v data retention mode t r ce v cc switching waveforms figure 3. read cycle no. 1 (address transition controlled) [12, 13] previous data valid data valid rc t aa t oha t rc address data out notes 10. v il (min) = ?2.0 v and v ih (max) = v cc + 1 v for pulse durations of less than 5 ns. 11. full device operation requires linear v cc ramp from v dr to v cc(min) > 50 ? s or stable at v cc(min) > 50 ? s. 12. device is continuously selected. oe , ce , bhe and/or ble = v il . 13. we is high for read cycle. [+] feedback
cy7c1021d document #: 38-05462 rev. *j page 8 of 16 figure 4. read cycle no. 2 (oe controlled) [14, 15] switching waveforms (continued) 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd t dbe t lzbe t hzce high impedance i cc i sb oe ce address data out v cc supply bhe ,ble current notes 14. we is high for read cycle. 15. address valid prior to or coincident with ce transition low. [+] feedback
cy7c1021d document #: 38-05462 rev. *j page 9 of 16 figure 5. write cycle no. 1 (ce controlled) [16, 17] figure 6. write cycle no. 2 (ble or bhe controlled) switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw t data i/o address ce we bhe ,ble t hd t sd t bw t sa t ha t aw t pwe t wc t sce data i/o address bhe ,ble ce we notes 16. data i/o is high impedance if oe or bhe and/or ble = v ih . 17. if ce goes high simultaneously with we going high, the output remains in a high impedance state. [+] feedback
cy7c1021d document #: 38-05462 rev. *j page 10 of 16 figure 7. write cycle no. 3 (we controlled, oe low) switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw t sa t lzwe t hzwe data i/o address ce we bhe ,ble truth table ce oe we ble bhe io 0 ?io 7 io 8 ?io 15 mode power hxxxx high z high z power down standby (i sb ) l l h l l data out data out read ? all bits active (i cc ) l h data out high z read ? lower bits only active (i cc ) h l high z data out read ? upper bits only active (i cc ) l x l l l data in data in write ? all bits active (i cc ) l h data in high z write ? lower bits only active (i cc ) h l high z data in write ? upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) l x x h h high z high z selected, outputs disabled active (i cc ) [+] feedback
cy7c1021d document #: 38-05462 rev. *j page 11 of 16 ordering information speed (ns) ordering code package diagram package type operating range 10 CY7C1021D-10VXI 51-85082 44-pin (400-mil) molded soj (pb-free) industrial cy7c1021d-10zsxi 51-85087 44-pin tsop type ii (pb-free) shaded areas contain advance information. cont act your local cypress sales representa tive for availability of these parts. ordering code definitions temperature range: i i = industrial pb-free package type: xx = v or zs v = 44-pin molded soj zs = 44-pin tsop type ii speed: 10 ns d = c9, 90 nm technology 1 = data width 16-bits 02 = 1-mbit density 1 = fast asynchronous sram family technology code: c = cmos marketing code: 7 = sram company id: cy = cypress c cy 1 - 10 xx 7 02 i d 1 x [+] feedback
cy7c1021d document #: 38-05462 rev. *j page 12 of 16 package diagrams figure 8. 44-pin molded soj (400-mil) v 44.4, 51-85082 51-85082 *c [+] feedback
cy7c1021d document #: 38-05462 rev. *j page 13 of 16 figure 9. 44-pin tsop z44-ii, 51-85087 package diagrams (continued) 51-85087 *c [+] feedback
cy7c1021d document #: 38-05462 rev. *j page 14 of 16 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable soj small outline j-lead sram static random access memory tsop thin small outline package ttl transistor-transistor logic we write enable symbol unit of measure c degree celsius mhz mega hertz a micro amperes s micro seconds ma milli amperes mm milli meter ms milli seconds ns nano seconds ? ohms % percent pf pico farad vvolts wwatts % percent [+] feedback
cy7c1021d document #: 38-05462 rev. *j page 15 of 16 document history page document title: cy7c1021d, 1-mbit (64 k 16) static ram document number: 38-05462 rev. ecn no. orig. of change submission date description of change ** 201560 swi see ecn advance information data sheet for c9 ipp *a 233695 rkf see ecn dc parameters modified as per eros (spec # 01-02165) pb-free offering in the ordering information *b 263769 rkf see ecn added data retention characteristics table added t power spec in switching characteristics table shaded ordering information *c 307601 rkf see ecn reduced speed bins to ?10 and ?12 ns *d 520647 vkn see ecn converted from preliminary to final removed commercial operating range added i cc values for the frequencies 83mhz, 66mhz and 40mhz updated thermal resistance table added automotive product information updated ordering information table changed overshoot spec from v cc +2v to v cc +1v in footnote #4 *e 802877 vkn see ecn changed commercial operating range i cc spec from 60 ma to 80 ma for 100mhz, 55 ma to 72 ma for 83mhz, 45 ma to 58 ma for 66mhz, 30 ma to 37 ma for 40mhz changed automotive operating range i cc spec from 100 ma to 120 ma for 83mhz, 90 ma to 100 ma for 66mhz, 60 ma to 63 ma for 40mhz *f 2751755 08/14/09 vkn/pyrs for 12 ns speed, changed i cc spec from 120 ma to 90 ma for 12 ns speed, changed i sb1 spec from 50 ma to 10 ma and i sb2 spec from 15 ma to 10 ma *g 2898399 03/24/2010 aju updated package diagrams *h 3109897 12/14/2010 aju added ordering code definitions . *i 3245199 04/30/2011 pras dislodged automotive information to new datasheet (001-68372). removed the note ?automotive product information is preliminary.? in page 3. added acronyms and units of measure . updated in new template. *j 3086499 06/07/2011 aju updated functional description (removed ?for best practice recommendations, refer to the cypress application note an1064, sram system guidelines.?). [+] feedback
document #: 38-05462 rev. *j revised june 7, 2011 page 16 of 16 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1021d ? cypress semiconductor corporation, 2004-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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